1. Field of the Invention
This invention relates to an improved method of analog-to-digital (A/D) conversion by successively approximating a comparison reference signal to an incoming analog signal.
2. Description of the Prior Art
Of all the techniques for A/D conversion in use today in data-acquisition systems, "successive approximations" is perhaps the most widely used. Such an A/D conversion is basically implemented by successively approximating a comparison reference signal to a sampled analog signal.
Prior to descriptions of this invention, a known prior art successive approximation technique will be discussed with reference to the drawings of FIGS. 1 through 4.
FIG. 1 shows in block diagram form a successive approximation A/D converter circuit to which this invention is also applicable.
In FIG. 1, an analog signal S.sub.A to be converted into proportional digital signals is applied through an input terminal 10 to a sample and hold circuit 12. The circuit 12 receives the analog signal and outputs sampled analog signals which are successively applied to one input of a comparator 14. The comparator 14 receives at the other input a comparison reference voltage V.sub.CR from a comparison reference voltage generator 16, and compares the two input signals for producing the comparison result. A successive approximation controller 18, coupled to the output of the comparator 14, successively generates an appropriate approximation control code depending on the comparison result. The generator 16 receives a reference voltage V.sub.R at its input terminal 20, and generates an appropriate comparison reference voltage V.sub.CR in response to the control code supplied from the controller 18. The digital equivalent of a sampled analog signal is derived after completion of the successive approximations. The conversion process will be discussed in detail later.
FIG. 2 shows an example of circuitry suited for use as the comparison reference voltage generator 16. It should be noted that this circuit is arranged to receive an approximation control code formed of only 3 bits for the purposes of explanation. In FIG. 2, the reference voltage V.sub.R is applied, through the terminal 20, to a voltage divider which consists of a plurality of resistors 31-38 arranged in series between the terminal 20 and ground. The resistors 31-38 respectively develop comparison reference voltages V.sub.CR1 -V.sub.CR8 and are assigned binary codes "111", "110", "101", "100", "011", "010", "001" and "000", respectively as shown. The approximation control code is applied from the controller 18 to the generator 16 via input terminals 24A, 24B and 24C. Connected directly or by way of inverters to the terminals 24A, 24B and 24C is a plurality of transfer gates (or switches) 41-54 each of which is opened in response to logic "1". The analog voltages at the resistors 31-44 are selectively derived from an output terminal 60 in response to the approximation control code applied to the terminal 24A, 24B and 24C. Assuming, by way of example, that the approximation control code applied to the input terminals 24A, 24B, and 24C is "100", then the transfer gates 41, 44, 46, 48, 50, 52 and 54 are opened and all the other gates are closed and thus makes an electrical connection between the resistor 34 and the output terminal 60 by way of the gates 50, 44 and 41. Therefore, the proportional analog voltage V.sub.CR4 developed at the resistor 34 is selected and applied to the other input of the comparator 14 through the output terminal 60.
The prior art "successive approximations" will be discussed with reference to FIG. 3 wherein the schematically illustrated voltage divider (the resistors 31-38) is the same as in FIG. 2. The controller 18 (FIG. 1) generates a first approximation control code "100", wherein all the bits are set to logic "0" except for MSB (Most Significant Bit) which is set to logic "1". The generator 16 outputs, in response to the control code "100", the first comparison reference voltage V.sub.CR4 developed at the resistor 34. The reference voltage V.sub.CR4 equals V.sub.R /2 or a potential in the vicinity thereof. If the sampled analog signal is greater than V.sub.CR4, the control code is so changed that the next MSB is set to logic "1" while maintaining logic "1" at the MSB and thus becomes "110". The control code "110" allows the generator 16 to output the comparison reference voltage V.sub.CR2 developed at the resistor 32. If the analog signal is further greater than V.sub.CR2, the control code changes to "111" by setting logic "1" to the third MSB while maintaining the other bit states. If the analog signal is still further greater than V.sub.CR1, the control code "111" will be deemed the digital equivalent of the incoming analog signal. If the analog signal is less than V.sub.CR1, then the control code "110" is the digital equivalent of the analog signal. Contrarily, if the analog signal is less than V.sub.CR2, the control code changes to "101" by setting logic "0" to the next MSB and logic "1" to third MSB (viz., LSB). If the analog signal is greater than V.sub.CR3, the control code "101" will be deemed the digital equivalent of the analog signal. If the analog signal is less than V.sub.CR3, then the binary code "100" is the digital equivalent of the incoming signal in this particular example.
However, if the analog signal is less than V.sub.CR4, the control code is changed to "010" by shifting logic "1" to the next MSB. The generator 16 outputs a comparison reference voltage V.sub.CR6 developed at the resistor 36. If the analog signal is greater than V.sub.CR6, the control code changes to "011" by setting logic "1" at the third MSB (viz., LSB) while maintaining the other bit states. If the analog signal is further greater than V.sub.CR5, the control code "011" will be deemed the digital equivalent of the incoming analog signal. If the analog signal is less than V.sub.CR5, then the control code "010" is the digital equivalent of the analog signal. On the other hand, if the analog signal is less than V.sub.CR6, the control code changes to "001" by shifting logic "1" to the third MSB (or LSB). If the analog signal is greater than V.sub.CR7, the binary code " 001" will be deemed the digital equivalent of the analog signal. If the analog signal is less than V.sub.CR7, then the binary code "000" is the digital equivalent of the incoming signal in this particular example.
It is understood that with this known method of A/D conversion, any analog signals having potential less than V.sub.CR7 are converted into a digital "000", thus limiting the precision of the A/D conversion when the analog signal is in the vicinity of zero potential. Since it is highly desirable that the analog signals in the vicinity of zero level be exactly converted to either "001" or "000", this problem should be avoided.
One attempt to solve the above drawback involves the technique of assigning the resistors 32-38 and ground digital values "111", "110", "100", "011", "010", "001" and "000", respectively as shown in FIG. 4. However, this means that the resistor 31 should not be selected in the successive approximations or the transfer gate 47 (FIG. 2) should be removed and gives rise to the drawback that readily available IC chips cannnot be used and that a special (and therefore expensive) chips must be manufactured.
We have discussed the drawbacks of the prior arts wherein the digital output has only 3 bits, but the same discussions are ture of the case in which a digital output has more than 3 bits.